We are not using the JTAG interface.
The data sheet implies that I need to put a pull-up on TMS & TDI and a pull-down on Trst_n guess this is for when using the JTAG interface
But Since I am not using this interface, do I need to leave these signals floating ?
I intend on putting a pull-up TDI, TCK,TMS & Trst_n
Can you comment on this
· Do I need them ?
· As a min, what should I pull-up/pull-down
Do I need to put any filtering on the 3V3 supply to the part as it has analog circuits inside, ie a ADC
Thanks
Hello Adrian, I am a TI factory applications engineer supporting the UCD90120.
If one were using the JTAG interface, then pullups on TMS and TDI along with a pulldown on TRST (bar) would be appropriate. Since TMS, TDI, TCK, TDO also serve as GPIO pins pull them to the preferred "high impedance" level if you are using them. It is good practice to pulldown TRST (bar) with a 10K resistor.
Listed below is the recommended power supply filtering for the UCD90120:
Layout guidelines The thermal pad provides a thermal and mechanical interface between the device and the printed circuit board (PCB). While device power dissipation is not of primary concern, a more robust thermal interface can help the internal temperature sensor provide a better representation of PCB temperature. Connect the exposed thermal pad of the PCB to the device V
Layout guidelines
The thermal pad provides a thermal and mechanical interface between the device and the printed circuit board (PCB). While device power dissipation is not of primary concern, a more robust thermal interface can help the internal temperature sensor provide a better representation of PCB temperature. Connect the exposed thermal pad of the PCB to the device V
SS pins and provide at least a 4 x 4 pattern of PCB vias to connect the thermal pad and VSS pins to the circuit ground on other PCB layers. For supply voltage decoupling, provide power supply pin bypass to the device as follows:
For supply voltage decoupling, provide power supply pin bypass to the device as follows:
·
0.1F, X7R ceramic in parallel with 0.01F, X7R ceramic at pin 47 (BPCAP)
0.1F, X7R ceramic in parallel with 4.7F, X5R ceramic at pin 44 (V33D)
0.1F, X7R ceramic at pin 7 (V33DIO)
0.1F, X7R ceramic in parallel with 4.7F, X5R ceramic at pin 46 (V33A)
Depending on use and application of the various GPIO signals used as digital outputs, some impedance control may be desired to quiet fast signal edges. For example, when using the FPWM pins for fan control or voltage margining the pin will be configured as a digital “clock” signal. Route these signals away from sensitive analog signals. It is also good design practice to provide a series impedance of 20-33 ohms at the signal source to slow fast digital edges.
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